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unisonic technologies co., ltd 7106 cmos ic www.unisonic.com.tw 1 of 18 copyright ? 2011 unisonic technologies co., ltd qw-r502-018.e 3? digit, lcd display, a/d converters ? description the utc 7106 is a high performance, low power,3? digits a/d converter. included are seven segm ent decoders, display drivers, a reference, and a clock. the utc 7106 is designed to interface with a liquid crystal display (lcd) and includes a multiplexed backplane drive. the utc 7106 bring together a combination of high accuracy, versatility, and true economy. it f eatures auto zero to less than 10 v, zero drift of less than 1 v/c, input bias current of 10pa (max), and rollover error of less than one count. true differential inputs and reference are useful in all system, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type trans ducers. finally, the true economy of single power supply operation, enables a high performance panel meter to be built with the addition of only 10 passive components and a display. ? features *guaranteed zero reading for 0v input on all scales *true polarity at zero for precise null detection *1pa typical input current *true differential input an d reference, direct drive lcd display *low noise-less than 15 vp-p *on chip clock and reference *low power dissipation-typically less than 10mw *no additional active circuits required *enhanced display stability ? ordering information ordering number package packing lead free halogen free 7106l-d40-t 7106g-d40-t dip-40 tube 7106l-r40-r 7106g-r40-r ssop-40 tape reel 7106l-r40-t 7106g-r40-t ssop-40 tube 7106L-QM1-Y 7106g-qm1-y qfp-44 tray
7106 cmos ic unisonic technologies co., ltd 2 of 18 www.unisonic.com.tw qw-r502-018.e ? pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 dip- 40/ssop-40 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 (1000) ab4 pol (minus) osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - common in hi in lo a-z buff int v- g2(10 s) , c3 a3 g3 bp (100 s) , nc g2 c3 a3 g3 bp/gnd pol ab4 e3 f3 b3 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b1 c1 d1 v+ osc 1 osc 2 nc osc 3 test nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 (1 s) , (10 s) , (100 s) , mqfp - 44
7106 cmos ic unisonic technologies co., ltd 3 of 18 www.unisonic.com.tw qw-r502-018.e ? absolute maximum ratings (t a =25c) parameter symbol ratings unit supply voltage (v+ ~ v-) v dd 15 v analog input voltage (either input) (note 1) v i,ang v+ ~ v- v reference input voltage (either input) v i,ref v+ ~ v- v junction temperature t j 150 c operating temperature t opr 0 ~ +70 c storage temperature t stg -65 ~ +150 c note: 1 . input voltages may exceed the supply voltages provided the input current is limited to 100 a. 2. absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? thermal data parameter symbol ratings unit junction to ambient dip-40 ja 50 c/w ssop-40 70 qfp-44 75 ? electrical characteristics (t a =25 , f clock =48khz, measured by the circuit of fig.1) parameter symbol test conditions min typ max unit system performance zero input reading r z v in =0.0v, full scale=200mv -000.0 000.0 +000.0 digital reading ratio metric reading r r v in =v ref , v ref =100mv 999 999/1000 1000 digital reading rollover error e r -v in =+v in 200mv P difference in reading for equal positive and negative inputs near full scale 0.2 1 counts linearity l full scale=200mv or full scale=2v maximum devi- ation from best straight line fit (note 2) 0.2 1 counts common mode rejection ratio cmrr v cm =1v,v in =0v, full scale=200mv(note 2) 50 v/v noise v n v in =0v,full scale=200mv (peak-to-peak value not exceeded 95% of time) 15 v leakage current input il v in =0(note 2) 1 10 pa zero reading drift d zr v in =0, 0 ~ 70 (note 2) 0.2 1 v/c scale factor temperature coefficient t,s v in =199mv, 0 ~ 70 , (ext.ref.0ppm/ ) (note 2) 1 5 ppm/c end power supply character v+ supply current i ep v in =0 1.0 1.8 ma common pin analog common voltage v com 25k ? between common and positive supply (with respect to +supply) 2.7 3.05 3.3 v temperature coefficient of analog common t,a 25k ? between common and positive supply (with respect to +supply) 80 ppm/c
7106 cmos ic unisonic technologies co., ltd 4 of 18 www.unisonic.com.tw qw-r502-018.e ? electrical characteristics(cont.) parameter symbol test conditions min typ max unit display driver peak-to-peak segment drive voltage peak-to-peak backplane drive voltage v d,pp v+ ~ v-=9v(note 1) 4 5.5 6 v note : 1. back plane drive is in phase with segment drive fo r?off?segment,180 degrees out of phase for ?on? segment . frequency is 20 times conversion rate. average dc component is less than 50mv. 2. not tested, guaranteed by design.
7106 cmos ic unisonic technologies co., ltd 5 of 18 www.unisonic.com.tw qw-r502-018.e ? typical applications and test circuit (lcd display components selected for 200mv full scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - com in hi in lo a-z buff int v- g2 c3 a3 g3 bp utc 7106 display r3 c4 r1 r4 c1 r5 c5 in + - c2 r2 c3 display c1=0.1 f c2=0.47 f c3=0.22 f c4=100pf c5=0.02 f r1=24k r2=47k r3=91k r 4=1k r5=1m + - 9v
7106 cmos ic unisonic technologies co., ltd 6 of 18 www.unisonic.com.tw qw-r502-018.e ? design information summary sheet *oscillator frequency fosc=0.45/rc c osc >50pf, r osc >50k ? f osc (typ)=48khz *oscillator period t osc =rc/0.45 *integration clock frequency f clock =f osc /4 *integration period t int =1000(4/f osc ) *60/50hz rejection criterion t int /t 60hz or t int /t 50hz =integer *optimum integration current i int =4 a *full scale analog input voltage v infs (typ)=200mv or 2v *integrate esistor r int = v infs / i int *integrate capacitor c int =(t int )(i int )/ v int *integrator output voltage swing v int =(t int )(i int )/ c int *v int maximum swing (v- + 0.5v) 7106 cmos ic unisonic technologies co., ltd 7 of 18 www.unisonic.com.tw qw-r502-018.e ? typical integrator amplifier output waveform (int pin) ? detailed description analog section fig.1 shows the analog section for the utc 7106 . each measurement cycle is divided into three phases. they are(1) auto-zero(a-z), (2)signal inte grate (int)and (3) de-integrate(de). auto-zero phase during auto-zero three things happen. first, input high and low are disconnected from the pins and internally shorted to analog common. second, the reference capacitor is charged to t he reference voltage. third, a feedback loop is closed around the system to charge the auto-zero capacitor c az to compensate for offset voltages in the buffer amplifier, integrator, and comparat or. since the comparator is included in the loop, the a-z accuracy is limited only by the noise of the system. in any case, the offset referred to the input is less than 10 v. signal integrate phase during signal integrate, the auto-zer o loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins . the converter then integrates the differential voltage between in hi and in lo for a fixed time. this differential voltage can be within a wide common mode range: up to 1v from either supply. if, on the other hand, the input signal has no return with resp ect to the converter power supply, in lo can be tied to analog common to establish the correct common mode volt age. at the end of this phas e, the polarity of the integrated signal is determined. de-integrate phase the final phase is de-integrate, or re ference integrate. input low is inte rnally connected to analog common and input high is connected across the previously charged refer ence capacitor. circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. the time required for the output to return to zero is proportional to the i nput signal. specifically the digital reading displayed is: display count=1000( v in / v ref ). differential input the input can accept differential voltages anywhere with in the common mode range of the input amplifier, or specifically from 0.5v below the posit ive supply to 1v above the negative suppl y. in this range, the system has a cmrr of 86db typical. however, care must be exercised to assure the integrator output does not saturate. a worst case condition would be a large positive common mode volt age with a near full scale negative differential input voltage. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. for these critical applications t he integrator output swing can be reduced to less than the recommended 2v full scale swing with little loss of accuracy. the integrator output can swing to within 0.3v of either supply without loss of linearity.
7106 cmos ic unisonic technologies co., ltd 8 of 18 www.unisonic.com.tw qw-r502-018.e ? detailed description(cont.) differential reference the reference voltage can be generated any where within the power supply volt age of the converter. the main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. if there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positi ve signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. this difference in refe rence for positive or negative input voltage will give a roll-over error. however, by selecting the reference capacito r such that it is large enou gh in comparison to the stray capacitance, this error can be held to less than 0. 5 count worst case. (see component value selection) common in lo 30 32 31 v+ a-z int int a-z and de() v- fig.1 analog section de+ de- de- de+ a-z a-z ref hi ref lo c ref + stray c ref 34 36 35 33 28 1 2.8v - + - + - + 29 27 int a-z c int c az integrator r int v+ stray c ref - to digital section a-z comparator input low - + n input high 6.2v 10 a in hi buffer
7106 cmos ic unisonic technologies co., ltd 9 of 18 www.unisonic.com.tw qw-r502-018.e ? detailed description(cont.) analog common this pin is included primarily to set the common mode voltage for battery operation (utc 7106 ) or for any system where the input signals are floating with respect to t he power supply. the common pi n sets a voltage that is approximately 2.8v more negative than the positive supply. this is selected to give a minimum end-of-life battery voltage of about 6v. however, analog co mmon has some of the attributes of a reference voltage. when the total supply voltage is large enough to cause the zener to regulate(>7v), the common vo ltage will have a low voltage coefficient (0.001%/v), low output impedance ( 15 P ? ), and a temperature coefficient typically less than 80ppm/ . the utc 7106 , with its negligible dissipation, suffers from none of these problems. in either case, an external reference can easily be added, as shown in fig.2 analog common is also used as the input low return during auto-zero and de-integrate. if in lo is different from analog common, a common mode voltage exis ts in the system and is taken care of by the excellent cmrr of the converter. however, in some applications in lo will be set at a fixed known voltage(power supply common for instance).in this application, analog common should be ti ed to the same point, thus removing the common mode voltage from the converter. the same holds true for the re ference voltage. if reference can be conveniently tied to analog common, it should be since this removes t he common mode voltage from the reference system. within the ic, analog common is tied to an n-channel fe t that can sink approximatel y 30ma of current to hold the voltage 2.8v below the positive supp ly (when a load is trying to pull the common line positive). however, there is only 10 a of source current, so common may easily be tied to a more negative voltage thus overriding the internal reference. iz 6.8v zener v- v + v ref hi ref lo utc 7106 common ref lo ref hi utc 7106 v 20k 6.8k icl8069 v+ 1.2v reference figure 2b. figure 2 a. fig.2 using an external reference
7106 cmos ic unisonic technologies co., ltd 10 of 18 www.unisonic.com.tw qw-r502-018.e ? detailed description(cont.) test the test pin serves two function. on the utc 7106 it is coupled to the internally generated digital supply through a 500 ? resistor. thus it can be used as the negative supply for externally g enerated segment drivers such as decimal points or any other presentation the user may want to include on th e lcd display. fig.3 and 4 show such an application. no more than a 1ma load should be applied. the second function is a ?lamp test?. when test is pulled high (to v+) all segments will be turned on and the display should read ?1888?. the test pin wi ll sink about 15ma under these conditions. caution: in the lamp test mode, the segments have a constant dc voltage (no square-wave) . this may burn the lcd display if maintained for extended periods.
7106 cmos ic unisonic technologies co., ltd 11 of 18 www.unisonic.com.tw qw-r502-018.e ? detailed description(cont.) digital section fig.5 show the digital section for the utc 7106 , respectively. in the utc 7106 , an internal digital ground is generated from a 6v zener diode and a large p-channel sour ce follower. this supply is made stiff to absorb the relative large capacitive currents when the back plane(bp) voltage is switched. the bp frequency is the clock frequency divided by 800. for three readings/sec, this is a 60hz square wave with a nominal amplitude of 5v. the segments are driven at the same fr equency and amplitude and are in phase with bp when off, but out of phase when on. in all cases negligible dc voltage exists across the segments. lcd phase driver 7 segment decode 7 segment decode 7 segment decode latch 1000 s counter , 100 s counter , 10 s counter , 1 s counter , backplane 200 logic control 4 from comparator output * three inverters one inverter shown for clarity clock 40 39 38 osc 1 osc 2 osc 3 fig.5 digital section v th =1v 26 37 6.2v 500 test v- v+ 1 21 typical segment output segment output 2ma 0.5ma v+ internal digital ground internal digital ground * a b a b g f e c d a b g f e c d a b g f e c d to switch drivers
7106 cmos ic unisonic technologies co., ltd 12 of 18 www.unisonic.com.tw qw-r502-018.e ? detailed description(cont.) system timing fig.6 shows the clocking arrangement used in the utc 7106 . two basic clocking arrangements can be used: 1. fig.6a. an external oscillator connected to pin 40. 2. fig.6b. an r-c oscillator using all three pins. the oscillator frequency is divided by four before it clo cks the decade counters. it is then further divided to form the three convert-cycle phases. these are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero(1000 ~ 3000 counts). for signals less than full scale. auto-zero gets the unused portion of reference de-integrate. this makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. for three readings/second, an osc illator frequency of 48khz would be used. to achieve maximum rejection of 60hz pickup, the signal integrate cycle should be a mu ltiple of 60hz. oscillator frequencies of 240khz, 120khz, 80khz, 60khz, 48khz, 40khz, 33 1/3khz, etc . should be selected. for 50hz rejection, oscillator frequencies of 200khz, 100khz, 66 2/3khz, 50khz, 40khz, etc . would be suitable. note that 40khz (2.5 readings/second) will reject both 50hz and 60hz (also 400hz and 440hz). 40 39 38 test clock internal to part figure 6a 40 39 38 rc oscillator clock internal to part figure 6b r c fig.6 clock circuits 4 4 component value selection integrating resistor both the buffer amplifier and the integr ator have a class a output stage with 100 a of quiescent current. they can supply 4 a of drive current with negligible nonlinearity. the int egrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the pc board. for 2v full scale, 470k ? is near optimum and similarly a 47k ? for a 200mv scale. integrating capacitor the integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing(approximately. 0.3v fr om either supply).in the utc 7106 , when the analog common is used as a reference, a nomi naul+2v full scale integrator swing is fine. for three readings/second (48khz clock) nominal values for c int are 0.22 f and 0.10 f, respectively. of course , if different oscillator frequencies are used, these values should be changed in in verse proportion to maintain the same output swing. an additional requirement of the integr ating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. while other types of capacitors are adequat e for this application, polypropylene capacitors give undetectable errors at reasonable cost. auto-zero capacitor the size of the auto-zero capacitor has some influence on the noise of the system. for 200mv full scale where noise is very important, a 0.47 f capacitor is recommended. on the 2v scale, a 0.047 f capacitor increases the speed of recovery from overload and is adequate for noise on this scale.
7106 cmos ic unisonic technologies co., ltd 13 of 18 www.unisonic.com.tw qw-r502-018.e ? detailed description(cont.) reference capacitor a 0.1 f capacitor gives good results in most applications. however, where a large common mode voltage exists (i.e., the ref lo pin is not at analog common)and a 200mv scale is used, a larger value is required to prevent roll-ovre error. generally 1 f will hold the roll-over error to 0.5 count in this instance. oscillator components for all ranges of frequency a 91k ? resistor is recommended and the capaci tor is selected from the equation: f= 0.45/rc for 48khz clock (3 readings/sec), c=100pf. reference voltage the analog input required to generate full scale output (2000 counts) is: v in =2v ref .thus, for the 200mv and 2v scale, v ref should equal 100mv and 1v, respectively. however, in many applications where the a/d is connected to a transducer, there will exist a scale fa ctor other than unity between the input voltage and the digital reading. for instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662v. instead of dividing the input down to 200mv, the designer should use t he input voltage directly and select v ref =0.341v. suitable values for integrating resistor and capacitor would be 120k ? and 0.22 f. this makes the system slightly quieter and also avoids a divider network on the input.
7106 cmos ic unisonic technologies co., ltd 14 of 18 www.unisonic.com.tw qw-r502-018.e ? typical applications the utc 7106 may be used in a wide variety of configurations. the circuits which follow show some of the possibilities, and serve to illustrate the exc eptional versatility of these a/d converters. osc 1 osc 2 osc 3 test ref hi ref lo c ref+ c ref- common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 to pin 1 91k 100pf 0.1 f 0. 01 f 0. 47 f 1k 22k 1m 47k 0. 22 f set v ref =100mv 9v in + - + - to display to backplane values shown are for 200mv full scale,3 readings/sec.,floating supply voltage(9v battery). fig.7 using the internal reference
7106 cmos ic unisonic technologies co., ltd 15 of 18 www.unisonic.com.tw qw-r502-018.e ? typical applications(cont.)
7106 cmos ic unisonic technologies co., ltd 16 of 18 www.unisonic.com.tw qw-r502-018.e ? typical applications(cont.) osc 1 osc 2 osc 3 test ref hi ref lo c ref+ c ref- common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 to pin 1 91k 100pf 0.1 f 0. 47 f 100k 1m 47 k 0. 22 f scale factor adjust 9v to display a sillicon diode - connected transistor has a temper ature coefficient of about -2 mv / calibration is achieved by placing the s ensing transistor in ice water and adjusting zeroing potentiometer for a 00.0 . 0 reading. the sensor should then be placed in water and the scale - factor potentiometer adjusted for a 100.0 reading fig.9 used as a digital centigrade thermometer 0.01 f 100k 220 k 22k zero adjust silicon npn mps 3704 or similar to backplane . the boiling
7106 cmos ic unisonic technologies co., ltd 17 of 18 www.unisonic.com.tw qw-r502-018.e ? typical applications(cont.) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol osc1 osc2 osc3 test ref hi ref lo cref+ cref- common in hi in lo a-z buff int v- g2 c3 a3 g3 bp v+ to logic v dd o/range u/range cd4077 v- to logic gnd fig.10 circuit for developing underrange and overrange from utc 7106 outputs
7106 cmos ic unisonic technologies co., ltd 18 of 18 www.unisonic.com.tw qw-r502-018.e ? typical applications(cont.) osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 to backplane to display 47k 0.47 f 0.22 f 10 f 9v + - 100pf (for optimum bandwidth) scale factor adjust (v ref =100mv for ac to rms) 1 f 470k 4.3k 10k 1n914 10k 1 f 100k + - 2.2m 5 f ac in to pin 1 22k 1k 91k 100pf 0.1 f test is used as a common-mode reference level to ensure compatiblity with most op amps. ca3140 1 f 10 f 0.22 f fig. 11 ac to dc converter with utc 7106 utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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